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TDA7590
Digital signal processing IC for speech and audio applications
Preliminary Data
Features

24-bit, fixed point, 120 MIPS DSP core Large on-board memory (128KW-24 bit) Host access to internal RAM through expansion port Access to external RAM (16Mw) through expansion port Integrated stereo, 18-bit Sigma-DELTA A/D and 20-bit D/A converters Programmable CODEC sample rate up to 48KHz On-board PLL for core clock and converters External flash / SRAM memory bank management I2C and SCI serial interface for external control 2 ESSI interface JTAG interface Host interface 144-pin TQFP, 0.50mm pitch Automotive temperature range (from -40C to +85C)
TQFP144
Nevertheless, the embedded CODECs bandwidth and the generic processing engine allow to proceed also full-band audio signals. The large amount of on-chip memory (128 Kwords), together with the 16 Mwords external memory addressable and the 32 general purpose I/O pins permit to build a DSP-system avoiding the usage of an additional Microcontroller. The presence of serial and parallel interfaces allows easy connection with external devices including CODECs, DSPs, Microprocessors and Personal Computers. In particular, the Debug/JTAG interface permits the on-chip emulation of the firmware developed. Further, the presence of the Timers and Watchdog Block makes TDA7590 suitable for PWM processing and allows the integration of a system Watchdog.
Description
The TDA7590 is a high performances, fully programmable 24-bit, 120 MIPS. Digital Signal Processor (DSP), designed to support several speech and audio applications, as Automatic Speech Recognition, Speech Synthesis, MP3 Decoding, Echo and Noise Cancellation.
Applications
Real time digital speech and audio processing: speech recognition, speech synthesis, speech compression, echo canceling, noise canceling, MP3 decoding.
Order codes
Part number E-TDA7590(1) E-TDA7590TR(1)
1. ECOPACK(R) (see Chapter 9)
Package TQFP144 (20x20x1.0 exposed pad down)
Packing Tube Tape & Reel
April 2006
Rev 1
1/40
www.st.com 40
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
TDA7590
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 2.3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 CODEC (ADC/DAC) Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical characteristics for I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6 7
24 bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Serial Audio Interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Host Interface (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ESSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 EOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timers and Watchdog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CODEC CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1 Benchmarking Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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TDA7590
Contents
9 10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/40
Block diagram
TDA7590
1
Figure 1.
Block diagram
Block diagram
2 Channel Codec
ESSI
ESSI/12C
SCI
HOST i/f
Triple Timer
SAI/CCT
PLL Clock Oscillator
sclk
rclk
YRAM 68/64/56/48K x 24
XRAM 4/8/16/14K x 24
FLEX RAM 40K x 24
PRAM PROM 16K x 24
EDB
Expansion Port
EAB
DDB
DAB
YDB
XDB
YAB
XAB
MOZART core
EBUG Interface
120MIPs, 32 GPIOs
4/40
PAB
TDA7590
Pin description
2
2.1
Figure 2.
Pin description
Pin connection
Pin connection (top view)
SC11 SC12 TDO TMS TCK TDI TRSTN IRQD IRQC IRQB IRQA DB23 DB22 DB21 IOVSS IOVDD DB20 COREVSS COREVDD DB19 DB18 DB17 DB16 DB15 IOVSS IOVDD DB14 DB13 DB12 DB11 DB10 DB9 IOVSS IOVDD DB8 DB7 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 SRD1 STD1 SC02 SC01 DE_N NMI SRD0 IOVDD IOVSS STD0 SC10 SC00 RXD TXD SCLK SCK1 SCK0 RESET SCANEN TESTEN COREVDD COREVSS TIO0 VSSSUB DAC1 DACOM DACOP REF0 CODEC_VDD CODEC_VSS ADC1 ADCOM ADCOP IOVDD IOVSS EXTDACLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
DB6 DB5 DB4 DB3 COREVSS COREVDD DB2 DB1 DB0 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 IOVSS IOVDD AB11 AB10 COREVSS COREVDD AB9 AB8 AB7 AB6 IOVSS IOVDD AB5 AB4 AB3 AB2 IOVSS IOVDD AB1
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
AB0 BG AA0 AA1 OEN WEN IOVSS IOVDD BB BR AA2 AA3 HAD0 HAD1 HAD2 HAD3 COREVSS COREVDD HAD4 HAD5 HAD6 HAD7 HAS HA8 HA9 HCS IOVSS IOVDD HREQ HACK HRW HDS PLL_VSS PLL_VDD XTO XTI
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Pin description
TDA7590
2.2
Table 1.
N 1 2 3 4 5 6 7 8 9 10 11
Pin function
Pin function
Name SRD1/TI02 STD1 SC02 SC01 DE_N NMI_N SRD0 IOVDD IOVSS STD0 SC10/SCL Type I/O I/O I/O I/O I/O I I/O I I I/O I/O Description Serial Receive Data. Serial input data for receiver. Timer 2 input/output. Serial Transmit Data. Serial output data from transmitter. Serial Control 2.Transmitter frame sync only in asynchronous mode, transmitter and receiver frame sync in synchronous mode. Serial Control 1. Receive frame sync in asynchronous mode, output from transmitter 2 or serial flag 1 in synchronous mode. Test Data Output(Input/Output). Debug Request input and Acknowledge output. Non-maskable interrupt/ PINIT. Used to enable the PLL during RESET and as a non-maskable interrupt at all other times. Serial Receive Data. Serial input data for receiver. IO Power Supply. IO Ground. Serial Transmit Data. Serial output data from transmitter. ESSI1 Serial Control 0. Receive clock in asynchronous mode, output from transmitter or serial flag in synchronous mode. I2C SCL. Serial Clock Line. Serial Control 0. Receive clock in asynchronous mode, output from transmitter 1 or serial flag 0 in synchronous mode. SCI Receive Data. Receives byte-oriented serial data. SCI Read Enable. Transmits serial data from SCI transmit shift register. SCI Serial Clock. Input or ouput clock from which data is transferred in synchronous mode and from which the transmit and/or receive baud rate is derived in asynchronous mode. Serial Clock. Serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and transmitter in synchronous mode. Timer 1 input/output. Serial Clock. Serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and transmitter in synchronous mode. System Reset. A low level applied to RESET_N input initializes the IC. SCAN Enable. When active with TESTEN also active, controls the shifting of the internal scan chains. Test Enable. When active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When SCANEN is also active, the scan chain shifting is enabled. Core Ground. Core Power Supply. Timer 0 input/output.
12 13 14 15
SC00 RXD TXD SCLK
I/O I/O I/O I/O
16
SCK1/TI01
I/O
17 18 19
SCK0 RESETN SCANEN
I/O I I
20 21 22 23
TESTEN COREVSS COREVDD TIO0
I I I I/O
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TDA7590 Table 1.
N 24 25 26 27 28 29 30 31 32 33 36 37 38 39 40 41
Pin description Pin function (continued)
Name VSSSUB DAC1 DAC0M DAC0P CODEC_VSS REF0 CODEC_VDD ADC1 ADC0M ADC0P EXTDACLK XTI XTO PLL_VDD PLL_VSS HDS Type I O O O I I I I I I I I O I I I/O Analog substrate isolation. DAC1 left single analog output. DAC0 negative right differential analog output. DAC0 positive right differential analog output. Voltage Ground. Codec Power Supply. Codec Reference. ADC1 left single analog input. DAC0 negative right differential analog inputs. DAC0 positive right differential analog inputs. External DAC clock. Optional external clock source from which LRCLK and SCLK can be generated. Crystal Oscillator Input. External Clock Input or crystal connection. Crystal Oscillator Output. Crystal Oscillator output drive. PLL Power Supply. PLL Ground Input . Host Data Strobe. Polarity programmable Host data strobe input for single strobe mode. Polarity programmable Host write strobe input for double strobe mode. Host Read/Write. Host read/write for single strobe bus mode. Polarity programmable Host read data strobe for double strobe mode. Host Acknowledge. Polarity programmable host interrupt acknowledge for single host request mode. Polarity programmable host receive request interrupt for double host request mode. Host Request. Polarity programmable host request interrupt for single host request mode. Polarity programmable host transfer request interrupt for double host request mode. IO Power Supply. IO Ground. Host Chip Select. Polarity programmable host chip select for non-multiplexed mode. Host address Line 10 for multiplexed mode. Host Address 9. Address line 9 in multiplexed mode otherwise address line 2 in non-multiplexed mode. Host Address 8. Address line 8 in multiplexed mode otherwise address line 1 in non-multiplexed mode. Host Address Strobe. Address Strobe for multiplexed bus or Address 0 for non multiplexed. Description
42
HRW
I/O
43
HACK
I/O
44 45 46 47
HREQ IOVDD IOVSS HCS
I/O I I I/O
48 49 50
HA9 HA8 HAS
I/O I/O I/O
7/40
Pin description Table 1.
N 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
TDA7590
Pin function (continued)
Name HAD[7] HAD[6] HAD[5] HAD[4] COREVDD COREVSS HAD[3] HAD[2] HAD[1] HAD[0] AA[3] AA[2] BR_N BB_N IOVDD IOVSS WEN_N OEN_N AA[1] AA[0] Type I/O I/O I/O I/O I I I/O I/O I/O I/O O O O I/O I I O O O O Description Host 8-bit data line 7. Host Data Bus and/or address lines when in multiplexed mode. Host 8-bit data line 6. Host Data Bus and/or address lines when in multiplexed mode. Host 8-bit data line 5. Host Data Bus and/or address lines when in multiplexed mode. Host 8-bit data line 4. Host Data Bus and/or address lines when in multiplexed mode. Core Power Supply. Core Ground. Host 8-bit data line 3. Host Data Bus and/or address lines when in multiplexed mode. Host 8-bit data line 2. Host Data Bus and/or address lines when in multiplexed mode. Host 8-bit data line 1. Host Data Bus and/or address lines when in multiplexed mode. Host 8-bit data line 0. Host Data Bus and/or address lines when in multiplexed mode. Address Attributes line 3.Port A address attributes/chip select pins with programmable polarity. Address Attributes line 2.Port A address attributes/chip select pins with programmable polarity. Bus Request. Asserted when Port A requires bus mastership to perform offchip accesses. Bus Busy. Asserted by Port A when bus_busy_in_n is negated and BG_N is asserted. IO Power Supply. IO Ground. Write Enable. Output Enable. Address Attributes line 1.Port A address attributes/chip select pins with programmable polarity. Address Attributes line 0.Port A address attributes/chip select pins with programmable polarity. Bus Grant. When asserted, Port A becomes the bus master elect. Bus mastership is attained when bus busy is negated by the current bus master. Address Bus line 0. Port A external address bus. Address Bus line 1. Port A external address bus. IO Power Supply.
71 72 73 74
BG_N AB[0] AB[1] IOVDD
I O O I
8/40
TDA7590 Table 1.
N 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
Pin description Pin function (continued)
Name IOVSS AB[2] AB[3] AB[4] AB[5] IOVDD IOVSS AB[6] AB[7] AB[8] AB[9] COREVDD COREVSS AB[10] AB[11] IOVDD IOVSS AB[12] AB[13] AB[14] AB[15] AB[16] AB[17] AB[18] AB[19] DB[0] DB[1] DB[2] COREVDD COREVSS DB[3] DB[4] DB[5] DB[6] DB[7] Type I O O O O I I O O O O I I O O I I O O O O O O O O I/O I/O I/O I I I/O I/O I/O I/O I/O IO Ground. Address Bus line 2. Port A external address bus. Address Bus line 3. Port A external address bus. Address Bus line 4. Port A external address bus. Address Bus line 5. Port A external address bus. IO Power Supply. IO Ground. Address Bus line 6. Port A external address bus. Address Bus line 7. Port A external address bus. Address Bus line 8. Port A external address bus. Address Bus line 9. Port A external address bus. Core Power Supply. Core Ground. Address Bus line 10. Port A external address bus. Address Bus line 11. Port A external address bus. IO Power Supply. IO Ground. Address Bus line 12. Port A external address bus. Address Bus line 13. Port A external address bus. Address Bus line 14. Port A external address bus. Address Bus line 15. Port A external address bus. Address Bus line 16. Port A external address bus. Address Bus line 17. Port A external address bus. Address Bus line 18. Port A external address bus. Address Bus line 19. Port A external address bus. Data Bus line 0. Port A external data bus. Data Bus line 1. Port A external data bus. Data Bus line 2. Port A external data bus. Core Power Supply. Core Ground. Data Bus line 3. Port A external data bus. Data Bus line 4. Port A external data bus. Data Bus line 5. Port A external data bus. Data Bus line 6. Port A external data bus. Data Bus line 7. Port A external data bus. Description
9/40
Pin description Table 1.
N 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
TDA7590
Pin function (continued)
Name DB[8] IOVDD IOVSS DB[9] DB[10] DB[11] DB[12] DB[13] DB[14] IOVDD IOVSS DB[15] DB[16] DB[17] DB[18] DB[19] COREVDD COREVSS DB[20] IOVDD IOVSS DB[21] DB[22] DB[23] IRQA IRQB IRQC IRQD TRSTN TDI TCK Type I/O I I I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I I I/O I I I/O I/O I/O I I I I I I I Description Data Bus line 8. Port A external data bus. IO Power Supply. IO Ground. Data Bus line 9. Port A external data bus. Data Bus line 10. Port A external data bus. Data Bus line 11. Port A external data bus. Data Bus line 12. Port A external data bus. Data Bus line 13. Port A external data bus. Data Bus line 14. Port A external data bus. IO Power Supply. IO Ground. Data Bus line 15. Port A external data bus. Data Bus line 16. Port A external data bus. Data Bus line 17. Port A external data bus. Data Bus line 18. Port A external data bus. Data Bus line 19. Port A external data bus. Core Power Supply. Core Ground. Data Bus line 20. Port A external data bus. IO Power Supply. IO Ground. Data Bus line 21. Port A external data bus. Data Bus line 22. Port A external data bus. Data Bus line 23. Port A external data bus. Interrupt Request line/ Mode control. Used as mode control during RESET and as interrupt request line at all other times. Interrupt Request line/ Mode control. Used as mode control during RESET and as interrupt request line at all other times. Interrupt Request line/ Mode control. Used as mode control during RESET and as interrupt request line at all other times. Interrupt Request line/ Mode control. Used as mode control during RESET and as interrupt request line at all other times. Test Reset. JTAG output pin for serial data out from debug interface. Test Data Input. JTAG input pin for serial data input for debug interface. Test Clock. JTAG input pin for clocking debug interface.
10/40
TDA7590 Table 1.
N 141 142 143
Pin description Pin function (continued)
Name TMS TDO SC12 Type I O I/O Description Test Mode Select. JTAG input pin for control of TAP Controller of debug interface. Test Data Output. JTAG output pin for serial data out from debug interface. Serial Control 2.Transmitter frame sync only in asynchronous mode, transmitter and receiver frame sync in synchronous mode. Serial Control 1. Receive frame sync in asynchronous mode, output from transmitter 2 or serial flag 1 in synchronous mode. I2C SDA. Serial Data Line.
144
SC11/SDA
I/O
2.3
Table 2.
Symbol Rth-j-pins
Thermal data
Thermal data
Parameter Thermal Resistance Junction to Pins Value 32 Unit C/W
11/40
Key parameters
TDA7590
3
3.1
Key parameters
Power consumption
Power consumption depends on application running and DSP clock frequency. Supply current values are measured and guaranteed at testing level by adopting the benchmarking program reported in Appendix 1. Table 3.
Symbol General fosc CORE_VDD Crystal frequency Operating voltage 1.62 3.0 3.0 3.0 1.8 3.3 3.3 3.3 16 1.98 3.6 3.6 3.6 150 50 -40 85 MHz V V V V mA mA C
Key parameters
Parameter Min. Typ. Max. Unit
CODEC_VDD Operating voltage IOVDD PLL_VDD IDD_1.8V IDD_3.3V Tamb DSP Core fdsp DSP clock frequency Operating voltage Operating voltage Supply current Supply current Operating temperature
120
MHz
ADC Single Ended Vpp THD/S (THD+N)/S DR ICL Maximum Input Range at ADC1 Total Harmonics Distortion to Signal (THD + Noise) to Signal Dynamic Range Interchannel Isolation -71 -70 75 -100 1.4 V dB dB dB dB
ADC Differential Vpp THD/S (THD+N)/S DR ICL Maximum Input Range at ADC0M-ADC0P Total Harmonics Distortion to Signal (THD + Noise) to Signal Dynamic Range Interchannel Isolation -65 -65 84 -100 2.8 V dB dB dB dB
DAC Single Ended Vpp THD/S (THD+N) Maximum Input Range at ADC1 Total Harmonics Distortion to Signal (THD + Noise) to Signal -64 -60 1.4 V dB dB
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TDA7590 Table 3.
Symbol DR ICL Dynamic Range Interchannel Isolation
Key parameters Key parameters (continued)
Parameter Min. Typ. 89 -100 Max. Unit dB dB
DAC Differential Vpp THD/S (THD+N)/S DR ICL Maximum Input Range at ADC1 Total Harmonics Distortion to Signal (THD + Noise) to Signal Dynamic Range Interchannel Isolation -58 -57 90 -85 2.8 V dB dB dB dB
3.1.1
CODEC (ADC/DAC) Test Description
Reported typical values (table 3. - ADC and DAC sections) have been measured at Lab level during product evaluation phase. General definitions and procedures are separately defined in following dedicated paragraphs.
Total Harmonic Distortion with Noise to Signal (THD+N)/S
THD+N is defined as the ratio of the total power of the second power and higher harmonic with noise components to the power of the fundamental for that signal. For THD+N measurement, choose the DSP analyzer in Digital analyzer with THD ratio as measurement option. Measure the THD+N value at -3dB amplitude of the input signal. First measure the THD+N value at 1Vrms which is 0dB reference and then measure the value at -3dB reference.
Dynamic Range (DR)
DR is defined as the level of THD+N measured when the input sine wave amplitude is so small that no harmonics apart from the fundamental tone are present in the output signal. This way THD+N becomes practically the ratio between the whole signal and noise floor, being a different way to express SNR. As a convention, at which no harmonics should be present in the output signal, it is fixed at -40dB of the full scale amplitude.
Crosstalk or Interchannel Isolation
A disturbance, caused by electromagnetic interference, along a circuit or a cable pair. An electric signal disrupts another signal in an adjacent circuit and can cause it to become confused and cross over each other. Crosstalk is measured by applying a signal -3dB amplitude of input signal at one channel (A) and no signal at an other channel (B), measuring the effect on this channel(B) because of the channel (A).
Total Harmonic Distortion to Signal (THD)/S
THD is defined as the ratio of the sum of only those components of the output signal which are harmonic of system input, after having removed the fundamental tone corresponding to the pure sine wave as input and the input signal.This measurement is done by using the Harmonic analyzer which can isolate up to 15th harmonic components on the acquired signal and report the sum of all of them, centering the fundamental tone on the frequency provided by the input signalgenerator. These measurements are performed at -3dB reference amplitude of input signal.
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Electrical specification
TDA7590
4
4.1
Table 4.
Electrical specification
Absolute maximum ratings
Absolute maximum ratings
Parameter 3.3V PLL Power Supply Voltage 3.3V CODEC Analog Power Supply 3.3V IO Power Supply 1.8V CORE Power Supply Input or Output Voltage Value -0.5 to 4 -0.5 to 4 -0.5 to 4 -0.5 to 2.2 -0.5 to (IOVDD +0.5) Unit V V V V V Symbol PLL_VDD CODEC_VDD IOVDD CORE_VDD IO_MAX
4.2
Table 5.
Symbol IOVDD Tj
Electrical characteristics for I/O pins
Reccomanded DC operating conditions
Parameter IO Power Supply Voltage Operating Junction Temperature Value 3 to 3.6 (*) -40 to 105 Unit V C
(*) All the specification are valid only within these recommended operating conditions.
Table 6.
Symbol Iil Iih Ioz
General interface electrical characteristics
Parameter Low level Input Current Without pullup device High level Input Current Without pulldown device Tri-state Output leakage Without pull up/down device Five Volt tolerant Tri-state Output leakage Without pull up/down device I/O Latch-up current Electrostatic Protection (HBM) Low level input voltage
(1))
Test Condition
Min.
Typ.
Max. 1 1 1
Unit A A A A mA V
IozFT I latchup Vesd Vil Vih Vhyst Vol Voh
1 V < 0V, V < Vdd leakage < 1mA 200 2000 0.8 2 0.4 Iol = XmA IOVDD - 0.15 0.15
V V V V V
High level input voltage(1) Schmitt trigger hysteresis(1) Low level output voltage
(1) (2) (3)
High level output voltage (1) (2) (3) Ioh = -XmA
1. TTL specifications only apply to the supply voltage range Vdd = 3.15V to 3.6V. 2. Takes into account 200mV voltagedrop in both supply lines. 3. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
14/40
TDA7590
24 bit DSP core
5
24 bit DSP core
The DSP Core is a general purpose 24-bit DSP. The main feature of the DSP Core are listed below:

120MHz Operating Frequency (120 MIPS) Fully Pipelined 24 x 24 Bit Parallel Multiplier-Accumulator Saturation/Limiting Logic 56-Bit Parallel Barrel Shifter Linear, Reverse Carry and Modulo Addressing Modes 24-bit Address Buses for Program, X and Y Data Spaces and DMA Memory-Expandible Hardware Stack Nested Zero-Overhead DO Loops Fast Interrupts Powerful JTAG Emulation Port Software WAIT and STOP Low Power Stand-by Modes Program Address Tracing Support Two 24-bit Data Moves in Parallel with Arithmetic Operations External Interrupts including Non-Maskable Interrupt Interrupts may be independently masked and prioritised Bit-Manipulation instructions can access any register or memory location On board support for DMA Controller
15/40
Memories
TDA7590
6
Memories
128K x 24 Bit RAM divided into 4 areas, Program RAM(PRAM), X data RAM(XRAM), Y data RAM(YRAM) and flexible allocation RAM(FLEX) as follows:

16K PRAM 40K FLEX RAM. FLEX RAM is accessed through the expansion port by the DSP core. External accessto the FLEX RAM is also supported. 72K RAM is allocated as XRAM and YRAM. Four configurations are supported: - - - - 4K XRAM and 68K YRAM 8K XRAM and 64K YRAM 16K XRAM and 56K YRAM 24K XRAM and 48K YRAM
16/40
TDA7590
DSP peripherals
7
7.1
DSP peripherals
Serial Audio Interface (SAI)
The SAI is used to communicate between the CODEC and the DSPs. In addition, digital audio can be directly input for processing. There is only one SAI found on the chip that can be accessed by either the DSP or the DMA controller. The main features of this block are listed below: - - - Slave Operating Modes, all clock lines can be inputs or outputs Transmit and Receive Interrupt Logic triggers on Left/Right data pairs Receive and Transmit Data Registers have two locations to hold left and right data
7.2
Serial Communication Interface (SCI)
The Serial Communication Interface provides a full duplex port for serial communication to other DSPs, microprocessors, and peripherals like modems. The interface supports the following features: - - - No additional logic for connection to other TTL level peripherals Asynchronous bit rates and protocols " High speed synchronous data transmission. Asynchronous protocol includes Multidrop mode for master/slave operation with Wakeup on Idle line and Wakeup on Address Bit capability, permitting the SCI to share a single line with multiple peripherals Transmit and Receive logic can operate asynchronously from each other. A programmable baud-rate generator which provide the transmit and receive clocks or functions as a general purpose timer.
- -
7.3
I2C Interface
The inter integrated-circuit bus is a simple bi-directional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C bus. Every component connected to the I2C bus has it s own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and/or transmitter depending on it s functionality.
7.4
Host Interface (HI)
The host interface is a system-on-chip module that permits connection to the data bus of a host processor. The HI is capable of driving 16 programmable external pins which can be configured as an 8 bit parallel port for direct connection to a host processor.
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DSP peripherals The key features of the host interface are:

TDA7590
8 bit parallel port "Full-duplex" Dedicated host register bank Dedicated Mozart Core DSP register core bank. Register banks map directly into Mozart X memory space 3 transfer modes: - - - host command Host to Mozart Core DSP Mozart Core DSP to host Software polled Interrupt DMA access by the Mozart Core DSP core
Access protocols: - - -

2+ wait states clock cycles per transfer Supported instructions: - - - Data transfer between Mozart core and external host using Mozart MOVE instruction Simple I/O service routine with bit addressing instructions IO service using fast interrupts with MOVEP instructions.
7.5
ESSI
The ESSI peripheral enables serial-port communication between the DSP core and external devices including CODECs, DSP, Microprocessors. The ESSI is capable of driving 12 programmable external pins which can be configured as GPIO ports C and D or ESSI pins. The key features of the ESSI are:

Independent receiver and transmitter Synchronous or Asynchronous channel modes Synchronous. Receiver and transmitter use same clock/sync Asynchronous. Receiver and transmitter may use separate clock/sync " Up to one transmitter enabled in asynchronous channel mode. Up to three transmitters enabled in synchronous channel mode. Normal mode. One word per period. Network Mode. Up to 32 words per period.

7.6
EOC
The Salieri Extended on-chip memory interface provides access to 40K of on-chip memory. The Mozart core will treat this memory as if it were external. Access by off-chip expansion bus masters is permitted. All accesses to the extended on-chip RAM are controlled by the extended on-chip memory control register. This register determines which combinations of the Address Attribute pins should be interpreted as accesses to the 40K of RAM.
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TDA7590
DSP peripherals
7.7
Timers and Watchdog Block
The Timers and Watchdog Block consists of a common 21-bit prescaler and three independent and identical general-purpose 24-bit timer/event counters, each with its own register set. Each timer has the following capabilities:

Uses internal or external clocking. Interrupts the Mozart after a specified number of events (clocks). Signals an external device after counting internal events. Triggers DMA transfers after a specified number of events (clocks) occurs. Connects to the external world through designated pins TIO[0-2] for timers 0-2. Input: Timer functions as an external event counter. Timer measures external pulse width/signal period. Output: Timer functions as a: - - - Timer Watchdog timer Pulse-width modulator.
When TIO is configured as an

7.8
PLL
The PLL generates the following clocks:

DCLK: DSP core clock DACLK: ADC and DAC clock LRCLK: left/right clock for the SAI and the CODEC SCLK: shift serial clock for the SAI and the CODEC
7.9
CODEC CELL
The main features of the CODEC cell are listed below:

20 bits stereo DAC, and 18bits ADC I2S format Oversampling ratio: 512 Sampling rates of 8 kHz to 48 kHz
The analog interface is in the form of differential signals for each channel. The interface on the digital side has the form of an SAI interface and can interface directly to an SAI channel and then to the DSP core. DCLK can be supplied either by the internal PLL or by external, to allow synchronization with external anal digital sources.
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Appendix 1
TDA7590
8
8.1
Appendix 1
Benchmarking Program
;********************************* FILE HEADER ********************************* ; ;Title: ; ;File Name: ; ;Author: ; ;Language: ; ;Project: ; ;Description: ; ; ; ; ; ; ; ;; ;******************************************************************************* ;*********************************** Equates *********************************** ;******************************************************************************* CODEC + TIMER + HI gpios + ESSI + SCI Salieri DSP2420 Core Assembler -full_func.asm Salieri CODEC/SAI Functionality Test
Npts Ntaps
equ equ
20 4
;-----------------------------------------------------------------------; EQUATES for I/O Port Programming
;------------------------------------------------------------------------
; M_HDR M_HDDR M_PCRC M_PRRC M_PDRC M_PCRD M_PRRD M_PDRD M_PCRE M_PRRE M_PDRE M_OGDB
Register Addresses EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFC9 $FFFFC8 $FFFFBF $FFFFBE $FFFFBD $FFFFAF $FFFFAE $FFFFAD $FFFF9F $FFFF9E $FFFF9D $FFFFFC ; PS- Host port GPIO data Register ; PS- Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ; Port C GPIO Data Register ; Port D Control register ; Port D Direction Data Register ; Port D GPIO Data Register ; Port E Control register ; Port E Direction Register ; Port E Data Register ; OnCE GDB Register
;-----------------------------------------------------------------------; EQUATES for Exception Processing
;-----------------------------------------------------------------------; Register Addresses IPR_C EQU $FFFFFF ; Interrupt Priority Register Core
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TDA7590
IPR_P EQU $FFFFFE ; Interrupt Priority Register Peripheral
Appendix 1
; SAI interrupt Vectors SAI_ROF SAI_TUF SAI_RDR SAI_TDE EQU EQU EQU EQU $070 $072 $074 $076 ; Receiver Overflow ; Transmitter Underflow ; Receiver Data Ready ; Transmitter Data Empty
; Timer interrupt Vector Timer0_tcf Timer0_tof Timer1_tcf Timer1_tof Timer2_tcf Timer2_tof equ equ equ equ equ equ $24 $26 $28 $2A $2C $2E ; Timer0 Compare ; Timer0 Overflow ; Timer1 Compare ; Timer1 Overflow ; Timer2 Compare ; Timer2 Overflow
; SCI Interrupt Vectors SCI_REC SCI_REC_E SCI_TRANS SCI_IDLE SCI_TIMER EQU EQU EQU EQU EQU $000050 $000052 $000054 $000056 $000058 ; SCI receive data ; SCI receive data with exception status ; SCI transmit data ; SCI idle line ; SCI timer
;;; Bit Definition for SCI_SSR FRAMING EQU 6
RESET
EQU
$000000
; Reset address location
;-----------------------------------------------------------------------; EQUATES for SAI (y memory)
;-----------------------------------------------------------------------SAI_RCS SAI_RX2 SAI_RX1 SAI_RX0 SAI_TCS SAI_TX2 SAI_TX1 SAI_TX0 EQU EQU EQU EQU EQU EQU EQU EQU $FFFFFF $FFFFFE $FFFFFD $FFFFFC $FFFFFB $FFFFFA $FFFFF9 $FFFFF8 ; SAI Receive Control/Status Register ; SAI Channel 2 Receiver Data ; SAI Channel 1 Receiver Data ; SAI Channel 0 Receiver Data ; SAI Transmit Control/Status Register ; SAI Channel 2 Transmitter Data ; SAI Channel 1 Transmitter Data ; SAI Channel 0 Transmitter Data
;;; Bit Definitions for M_RCS ROFCL RDR ROFL ;Reserved RXIE RDWJ RREL RCKP RLRS RDIR RWL1 RWL0 ;Reserved RMME R2EN R1EN R0EN EQU EQU EQU EQU 3 2 1 0 ; Receiver Master Mode Enable ; Receiver 2 enable ; Receiver 1 enable ; Receiver 0 enable EQU EQU EQU EQU EQU EQU EQU EQU 12 11 10 9 8 7 6 5 ; Receiver Interrupt Enable ; Receiver Data Word Justification ; Receiver Relative Timing ; Receiver Clock Polarity ; Receiver Left Right Selection ; Receiver Data Shift Direction ; Receiver Word Length Control 1 ; Receiver Word Length Control 0 EQU EQU EQU 16 15 14 ; Receiver Data Overflow Clear ; Receiver Data Ready ; Receiver Data Overflow
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Appendix 1
;;; Bit Definitions for M_TCS TUFCL TDE TUFL ;Reserved TXIE TDWE TREL TCKP TLRS TDIR TWL1 TWL0 ;Reserved TMME T2EN T1EN T0EN EQU EQU EQU EQU 3 2 1 0 ; Transmitter Master Mode Enable ; Transmitter 2 enable ; Transmitter 1 enable ; Transmitter 0 enable EQU EQU EQU EQU EQU EQU EQU EQU 12 11 10 9 8 7 6 5 ; Transmitter Interrupt Enable ; Transmitter Data Word Justification ; Transmitter Relative Timing ; Transmitter Clock Polarity ; Transmitter Left Right Selection ; Transmitter Data Shift Direction ; Transmitter Word Length Control 1 ; Transmitter Word Length Control 0 EQU EQU EQU 16 15 14 ; Transmitter Data Overflow Clear ; Transmitter Data Ready ; Transmitter Data Overflow
TDA7590
;-----------------------------------------------------------------------; EQUATES for CODEC
;-----------------------------------------------------------------------CODEC_CSR EQU $FFFFCB ; CODEC Control Register Address
;;; Bit Definitions for CODEC GADCL_0 GADCL_1 GADCL_2 GADCR_0 GADCR_1 GADCR_2 GDACL_0 GDACL_1 GDACL_2 GDACR_0 GDACR_1 GDACR_2 MUTEDAC PDNDAC PDNADC N_RST EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ; ADC Left ; ADC Left ; ADC Left Gain Bit 0 Gain Bit 1 Gain Bit 2
; ADC Right Gain Bit 0 ; ADC Right Gain Bit 1 ; ADC Right Gain Bit 2 ; DAC Left ; DAC Left ; DAC Left Gain Bit 0 Gain Bit 1 Gain Bit 2
; DAC Right Gain Bit 0 ; DAC Right Gain Bit 1 ; DAC Right Gain Bit 2 ; Mute DAC - Active Hi, Reset Val = 1 ; Power down DAC - Active Hi, Reset Val = 0 ; Power down ADC - Active Hi, Reset Val = 0 ; Asynchronoue Reset - Active Lo, Reset Val = 1
;-----------------------------------------------------------------------; EQUATES for PLL
;-----------------------------------------------------------------------PLL_CSR PLL_FCR PLL_CLKCTL EQU EQU EQU $FFFFD7 $FFFFD6 $FFFFD5 ; PLL Control/Status Register ; PLL Fractional Register ; PLL Clock Control Register
;;; Bit Definitions for PLL_CSR IDF0 IDF1 IDF2 IDF3 IDF4 ; Reserved EQU EQU EQU EQU EQU 0 1 2 3 4 ; Input Divide Factor 0 ; Input Divide Factor 1 ; Input Divide Factor 2 ; Input Divide Factor 3 ; Input Divide Factor 4
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TDA7590
LOCK OUTLOCK MF0 MF1 MF2 MF3 MF4 MF5 MF6 PLLIE PWRDN DITEN FRACEN PEN EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ; PLL Lock Indication bit ; PLL Lost Lock bit ; Multiplication bit 0 ; Multiplication bit 1 ; Multiplication bit 2 ; Multiplication bit 3 ; Multiplication bit 4 ; Multiplication bit 5 ; Multiplication bit 6 ; PLL interrupt enable ; PLL power down ; Dither Enable ; PLL Fractional-N function enable ; PLL Enable
Appendix 1
;;; Bit Definitions for PLL_CLKCNTL DSPDF0 DSPDF1 DSPDF2 DSPDF3 ; Reserved DCKSRC EQU 6 ; DSP clock source ; DACLKEN MFSDF0 MFSDF1 MFSDF2 MFSDF3 MFSDF4 MFSDF5 MFSDF6 SEL0 SEL1 SEL2 DSP_XTI EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 7 8 9 10 11 12 13 14 15 16 17 18 0->XTI/(DSPDF3:0 + 1) 1->VCO/(DSPDF3:0 + 1) EQU EQU EQU EQU 0 1 2 3 ; DSP clock divider factor 0 ; DSP clock divider factor 1 ; DSP clock divider factor 2 ; DSP clock divider factor 3
; Enable bit for oversampling clock ; Oversampling multiple bit 0 ; Oversampling multiple bit 1 ; Oversampling multiple bit 2 ; Oversampling multiple bit 3 ; Oversampling multiple bit 4 ; Oversampling multiple bit 5 ; Oversampling multiple bit 6 ; Sampling multiple select bit 0 ; Sampling multiple select bit 1 ; Sampling multiple select bit 2 ; DSP_XTI =0 -> Use VCO/DSPDF ; DSP_XTI =1 -> Use XTI for DCLK for DCLK
DAC_SEL XTLD
EQU EQU
19 20
; Selects between VCO and ext_dac_clk ; Disables the external crystal when set
;-----------------------------------------------------------------------; EQUATES for I/O Port Programming
;-----------------------------------------------------------------------; HDR HDDR PCRC PRRC PDRC PCRD PRRD PDRD PCRE PRRE PDRE OGDB Register Addresses EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFC9 $FFFFC8 $FFFFBF $FFFFBE $FFFFBD $FFFFAF $FFFFAE $FFFFAD $FFFF9F $FFFF9E $FFFF9D $FFFFFC ; PS- Host port GPIO data Register ; PS- Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ; Port C GPIO Data Register ; Port D Control register ; Port D Direction Data Register ; Port D GPIO Data Register ; Port E Control register ; Port E Direction Register ; Port E Data Register ; OnCE GDB Register
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Appendix 1
;-----------------------------------------------------------------------; EQUATES for GPIOs
TDA7590
;-----------------------------------------------------------------------;;; Register Addresses GPIOCTRL GPIODIR GPIODAT EQU EQU EQU $FFFFc4 $FFFFc8 $FFFFc9 ; Host Port Control Register ; GPIODIR register.(HI - HDDR) ; GPIODAT register.(HI - HDR)
;;; Bit Definitions for GPIO Direction Register GPIO0_DIR GPIO1_DIR GPIO2_DIR GPIO3_DIR GPIO4_DIR GPIO5_DIR GPIO6_DIR GPIO7_DIR GPIO8_DIR EQU EQU EQU EQU EQU EQU EQU EQU EQU $0 $1 $2 $3 $4 $5 $6 $7 $8
;;; Bit Definitions for GPIO Data Register GPIO0_DAT GPIO1_DAT GPIO2_DAT GPIO3_DAT GPIO4_DAT GPIO5_DAT GPIO6_DAT GPIO7_DAT GPIO8_DAT EQU EQU EQU EQU EQU EQU EQU EQU EQU $0 $1 $2 $3 $4 $5 $6 $7 $8
;-----------------------------------------------------------------------; EQUATES for Timer
;------------------------------------------------------------------------
M_TCSR0 M_TLR0 M_TCPR0 M_TCR0 M_TCSR1 M_TLR1 M_TCPR1 M_TCR1 M_TCSR2 M_TLR2 M_TCPR2 M_TCR2 M_TPLR M_TPCR
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
$FFFF8F $FFFF8E $FFFF8D $FFFF8C $FFFF8B $FFFF8A $FFFF89 $FFFF88 $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82
;Timer 0 Control/Status Register (TCSR0) ;Timer 0 Load Register (TLR0) ;Timer 0 Compare Register (TCPR0) ;Timer 0 Count Register (TCR0) ;Timer 1 Control/Status Register (TCSR1) ;Timer 1 Load Register (TLR1) ;Timer 1 Compare Register (TCPR1) ;Timer 1 Count Register (TCR1) ;Timer 2 Control/Status Register (TCSR2) ;Timer 2 Load Register (TLR2) ;Timer 2 Compare Register (TCPR2) ;Timer 2 Count Register (TCR2) ;Timer Prescaler Load Register (TPLR) ;Timer Prescaler Count Register (TPCR)
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------;ESSI 0 interrupt equates essi0_rdf essi0_roe essi0_rls equ equ equ $30 $32 $34 EQUATES for Enhanced Synchronous Serial Interface (ESSI)
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TDA7590
essi0_tde essi0_tue essi0_tls equ equ equ $36 $38 $3a
Appendix 1
;ESSI 1 interrupt equates essi1_rdf essi1_roe essi1_rls essi1_tde essi1_tue essi1_tls equ equ equ equ equ equ $40 $42 $44 $46 $48 $4a
;Register Addresses of ESSI0 M_TX00 M_TX01 M_TX02 M_TSR0 M_RX0 M_SSISR0 M_CRB0 M_CRA0 M_TSMA0 M_TSMB0 M_RSMA0 M_RSMB0 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFBC $FFFFBB $FFFFBA $FFFFB9 $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4 $FFFFB3 $FFFFB2 $FFFFB1 ; SSI0 Transmit Data Register 0 ; SSI0 Transmit Data Register 1 ; SSI0 Transmit Data Register 2 ; SSI0 Time Slot Register ; SSI0 Receive Data Register ; SSI0 Status Register ; SSI0 Control Register B ; SSI0 Control Register A ; SSI0 Transmit Slot Mask Register A ; SSI0 Transmit Slot Mask Register B ; SSI0 Receive Slot Mask Register A ; SSI0 Receive Slot Mask Register B
;Register Addresses of ESSI1 M_TX10 M_TX11 M_TX12 M_TSR1 M_RX1 M_SSISR1 M_CRB1 M_CRA1 M_TSMA1 M_TSMB1 M_RSMA1 M_RSMB1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFAC $FFFFAB $FFFFAA $FFFFA9 $FFFFA8 $FFFFA7 $FFFFA6 $FFFFA5 $FFFFA4 $FFFFA3 $FFFFA2 $FFFFA1 ; SSI1 Transmit Data Register 0 ; SSI1 Transmit Data Register 1 ; SSI1 Transmit Data Register 2 ; SSI1 Time Slot Register ; SSI1 Receive Data Register ; SSI1 Status Register ; SSI1 Control Register B ; SSI1 Control Register A ; SSI1 Transmit Slot Mask Register A ; SSI1 Transmit Slot Mask Register B ; SSI1 Receive Slot Mask Register A ; SSI1 Receive Slot Mask Register B
;-----------------------------------------------------------------------; EQUATES for SCI
;-----------------------------------------------------------------------PCRE_ADR PRRE_ADR PDRE_ADR SCR_ADR SCCR_ADR SRXH_ADR SRXM_ADR SRXL_ADR STXH_ADR STXM_ADR STXL_ADR STXA_ADR SSR_ADR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFF9F $FFFF9E $FFFF9D $FFFF9C $FFFF9B $FFFF9A $FFFF99 $FFFF98 $FFFF97 $FFFF96 $FFFF95 $FFFF94 $FFFF93 ; Serial Port Control Register ; Serial Port Direction Register ; Serial Port Direction Register ; SCI Control Register ; SCI Clock Control Register ; Serial Recieve Register high ; Serial Recieve Register mid ; Serial Recieve Register low ; Serial Transmit Register high ; Serial Transmit Register mid ; Serial Transmit Register low ; Serial Transmit Adress Register ; Serial Status Register
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Appendix 1
;-----------------------------------------------------------------------; EQUATES for Expansion Port
TDA7590
;-----------------------------------------------------------------------EXP_BCR EXP_AAR0 EXP_AAR1 EXP_AAR2 EXP_AAR3 EQU EQU EQU EQU EQU $FFFFFB $FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 $C00000 ; Bus Control Register address ; Address Attribte Register (AAR0) address ; Address Attribte Register (AAR1) address ; Address Attribte Register (AAR2) address ; Address Attribte Register (AAR3) address
EXT_RAM_STARTEQU
;-----------------------------------------------------------------------; EQUATES for Extended Memory
;-----------------------------------------------------------------------EOC_ADR EQU $FFFFCA
;******************************************************************************* ;***************************** Initialisation Values **************************
;*******************************************************************************
;------------------------------------------------------------------------------; CODEC Intitialisation values
;------------------------------------------------------------------------------; --- INIT_CCR ----------------------------------------------------------------; settings fro the CODEC Control Register ; INIT_CODEC_CSR ; ; ; ; ; ; ; ; EQU 321098765432109876543210 %000000001110011011011011 ; $00E6DB DACgain = 0dB - ADCgain = +0dBdB
011 --- GADCL[0:2] 011 ------ GADCR[0:2] 011 --------- GDACL[0:2] 011 ------------ GDACR[0:2] 0 --------------- MUTEDAC (1=Mute) 1 ---------------- PDNDAC (1=pwrdwn) 1 ----------------- PDNADC (1=pwrdwn) 1 ------------------ NRST (0=reset)
;------------------------------------------------------------------------------; SAI Intitialisation values
;-------------------------------------------------------------------------------
;--- INIT_RCS -----------------------------------------------------------------; settings for the Receiver Control/Status Register ; INIT_SAI_RCS ; ; ; ; ; ; ; ; ; ; ; ; ; ; EQU 321098765432109876543210 %000000000001000101001001 ; $000149
1 --- R0EN (0:Disbaled; 1:Enabled) 0 ---- R1EN (0:Disbaled; 1:Enabled) 0 ----- R2EN (0:Disbaled; 1:Enabled) 1 ------ RMME (1:Master mode; 0:Slave mode) 0 ------- Reserved 10 -------- RWL[0:1] (00:16; 01:24; 10:32) 0 ---------- RDIR (0:MSB 1st; 1:LSB 1st) 1 ----------- RLRS (0:LRCKR=0-LW; 1:LRCKR=0-RW) 0 ------------ RCKP (0:-ve ; 1:+ve) 0 ------------- RREL (0:trans-1st; 1:I2S) 0 -------------- RDWJ 1 --------------- RXIE (0:Disabled; 1:Enabled) 0 ---------------- Reserved 0 ----------------- ROFL
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TDA7590
; ; 0 ------------------ RDR 0 ------------------- ROFCL
Appendix 1
;--- INIT_TCS -----------------------------------------------------------------; settings for the Transmitter Control/Status Register ; INIT_SAI_TCS ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; EQU 321098765432109876543210 %000000000001010101001001 ; $000549 - non incrociato
1 --- T0EN (0:Disbaled; 1:Enabled) 0 ---- T1EN (0:Disbaled; 1:Enabled) 0 ----- T2EN (0:Disbaled; 1:Enabled) 1 ------ TMME (1:Master mode; 0:Slave mode) 0 ------- reserved 10 -------- TWL[0:1] (00:16; 01:24; 10:32) 0 ---------- TDIR (0:MSB 1st; 1:LSB 1st) 1 ----------- TLRS (0:LRCKR=0-LW; 1:LRCKR=0-RW) 0 ------------ TCKP (0:-ve ; 1:+ve) 1 ------------- TREL (0:trans-1st; 1:I2S) 0 -------------- TDWE 1 --------------- TXIE (0:Disabled; 1:Enabled) 0 ---------------- Reserved 0 ----------------- TUFL 0 ------------------ TDE 0 ------------------- TUFCL
;------------------------------------------------------------------------------; PLL Intitialisation values
;------------------------------------------------------------------------------IF 1 ; Settings per sci 115200
;--- PLL_CSR ------------------------------------------------------------------; settings for the PLL control register ; 321098765432109876543210
; settings for the PLL control register ; ;INIT_PLL_CSR INIT_PLL_CSR ; ; ; ; ; ; ; ; ; ; EQU EQU 321098765432109876543210 $0E0C00 %000011100000110000000000 ; $0E0C00
00000 --- IDF =0 (actual = IDF+1=1) 0 -------- RESERVED 0 --------- LOCK (read only; 0:out of lock) 0 ---------- OUTLOCK (read only; 0:in lock) 0001100 ----------- MF =12 (actual = MF + 1 = 13) 0 ------------------ PLLIE (0:intr disable) 0 ------------------- PWRDN (1:power down mode) 1 -------------------- DITEN (0:disable) 1 --------------------- FRACTN (0:disable) 1 ---------------------- PEN (1:PLL enable)
;--- FRACT --------------------------------------------------------------------; settings for the Fractional N part of the PLL ; ;INIT_PLL_FCR INIT_PLL_FCR EQU EQU 321098765432109876543210 $0034bd %000000000011010010111101 ; $0034bd
;
01110000101001 --- FRACT = 13501
;--- CLKCTL --------------------------------------------------------------------
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Appendix 1
; settings for the clock control register ; ;INIT_PLL_CLKCTL EQU INIT_PLL_CLKCTL EQU ; ; ; ; ; ; ; ; ; 321098765432109876543210 $018cc1 %000000011000001011000001 ; $018cc1
TDA7590
0001 --- DSPDF =1 (actual = DSPDF+1=3) 00 ------- TESTSEL 1 --------- DCKSRC (0:XTI; 1:FVCO) 1 ---------- DACLKEN (1: enable CODEC clocks) 0000010 ----------- MFSDF =2 (actual =MFSDF+1 = 3 ) 011 ------------------ SEL (000:128,001:256, 010:384, etc) 0 --------------------- DSP_XTI (0:vco/DSPDF; 1:xti) 0 ---------------------- DAC_SEL (0:vco/MFSDF; 1:ext_dac_clk) 0 ----------------------- XTLD (0:Enabled; 1:Disabled)
ENDIF
; Settings per sci 115200
;-----------------------------------------------------------------------; Timer Intitialisation values
;-----------------------------------------------------------------------;--- TCSR0 -------------------------------------------------------------------; settings for the Timer Control/Status Register ; INIT_TCSR0 INIT_TCSR1 INIT_TCSR2 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; EQU EQU EQU 321098765432109876543210 %000000001000101000000100 %000000001000101000000100 %000000001000101000000100 ; $8A04 ; $8A04 ; $8A04 mode0 / trm=1 / tce=1 / pce=1/ dir=out mode0 / trm=1 / tce=1 / pce=1/ dir=out mode0 / trm=1 / tce=1 / pce=1/ dir=out
xx ----------------------->[23-22]; unused 0 ---------------------->[21] 0 --------------------->[20] xxxx ----------------->[19-16] 0 ---------------->[15] x --------------->[14] 0 -------------->[13] 0 ------------->[12] 1 ------------>[11] x ----------->[10] 1 ---------->[ 9] 0 --------->[ 8] 0000 ----->[7-4] x ---->[ 3] 1 --->[ 2] 0 -->[ 1] 0 ->[ 0] TCIE TOIE TE TRM INV Tc[3-0] DO DI DIR PCE TCF TOF ; Timer Compare Flag ; Timer Overflow Flag ; unused ; Prescaler Clock Enable ; unused ; Data Output ; Data Input ; Direction ; unused ; Timer Reload Mode ; Inverter ; Timer Control = ; unused ; Timer Compare Interrupt Enable ; Timer Overflow Enable ; Timer Enable Mode0
;--- TLR0 -------------------------------------------------------------------; settings for the Timer Load Register INIT_TLR0 INIT_TLR1 INIT_TLR2 EQU EQU EQU $000000 $000000 $000000
;--- TCPR0 -------------------------------------------------------------------; settings for the Timer Compare Register ;INIT_TCPR0 ;INIT_TCPR1 ;INIT_TCPR2 INIT_TCPR0 INIT_TCPR1 EQU EQU EQU EQU EQU $000002 $000004 $000008 $000000 $000000
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TDA7590
INIT_TCPR2 EQU $000000
Appendix 1
;--- TPLR -------------------------------------------------------------------; settings for the clock control register ; ;INIT_TPLR INIT_TPLR ; ; ; ; 000000000010000000000-> EQU EQU 321098765432109876543210 %001000000000001111100111 %000000000000001111100111 x------------------------> 01----------------------> PS[1-0] ; $2003E7 source TIO0 / divider = 999+1 ; $0003E7 source internal / prescaler 999 ; ; ;
Reserved. Write to zero for future compatibility. Prescaler Source [00 internal / 01 external TIO0 / 10 external TIO0 / 11 external TIO0]
PL[20-0] ; Prescaler Preload Value200400
;------------------------------------------------------------------------------; Interrupt Initialisation Values
;------------------------------------------------------------------------------; settings for the Interrupt priority register - Core ; INIT_IPR_C EQU 321098765432109876543210 %000000000000000000000000 ; $000000
; settings for the Interrupt priority register - peripherals ; INIT_IPR_P ; ; ; ; ; ; ; ; ; ; ; ; EQU 321098765432109876543210 %000000000011111001000100 ; $29C4 glitch sull'uscita del dac
00---- HI 11------ ESSI0 00-------- ESSI1 11---------- SCI 11------------ TIMER 11 ------------- SAI 11 --------------- CODEC 00 ----------------- PLL 00 ------------------- Unknow 00 --------------------- I2C 00 ----------------------- SPI 00 ------------------------- EMI
;------------------------------------------------------------------------------; Expansion Port Intitialisation values
;------------------------------------------------------------------------------;--- INIT_AAR0 ----------------------------------------------------------------------; settings for the Address Attribute Register1 ; INIT_AAR0 ; ; ; ; ; ; ; ; ; ; EQU 321098765432109876543210 %110000000000010000010000 ; C00410 00 --- BAT (00: Synchronous SRAM; 01: SRAM; 10: DRAM; 11: Reserved)
0 ----- BAAP (0:AA1 active low; 1: AA1 active high) 0 ------ BPEN (0: P space disabled; 1: P space enabled) 1 ------- BXEN (0: X data space disabled; 1: X data space enabled) 0 -------- BYEN (0: Y data space disabled; 1: Y data space enabled) 0 --------- BAM (0: 8 LSB of address will appear on A0-A7; 1: 8 LSB of address will appear on A16-A23) 0 ---------- BPAC (0: packing disabled; 1: packing enabled) 0100 ----------- BNC 110000000000 --------------- BAC (Number of bits to compare; 1111, 1110, 1101 reserved) (Address to compare; BNC most significant)
;--- INIT_BCR -----------------------------------------------------------------------
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Appendix 1
; settings for the Bus Control Register ; INIT_BCR ;INIT_BCR ; ; ; ; ; ; ; ; EQU EQU 321098765432109876543210 %001100000010010000100001 ; 306E10 %000001111111110011100111 ; 30FE07 00111 --- BA0W (Area 0 wait states) 00000 -------- BA1W (Area 1 wait states) 111 ------------- BA2W (Area 2 wait states) 111 ---------------- BA3W (Area 3 wait states) 00000 ------------------- BDFW (Default area wait states) 0 ------------------------ BBS 0 ------------------------- BLH 0 -------------------------- BRH (0: ; 1: DSP is bus master READ ONLY) (0: ; 1: BLN always asserted) (0: ; 1: BRN always asserted)
TDA7590
;*******************************************************************************
; definitions addded by Paul Cassidy for salieri testbench TRIGGER_TUBE M_BCR M_AAR0 M_AAR1 M_AAR2 M_AAR3 EQU EQU EQU EQU EQU EQU $12002 $FFFFFB $FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 ; Bus Control Register ; Address Attribute 0 ; Address Attribute 1 ; Address Attribute 2 ; Address Attribute 3
;******************************************************************************* ;************************** Main Prog Starts Here ****************************** ;******************************************************************************* startp org p:$0 jmp start
sci_int org p:SCI_REC jsr INT_SCIR org p:SCI_TRANS jsr INT_SCIT org p:SCI_REC_E jsr INT_SCIE ; Interrupt SCI framing error ; Interrupt SCI transmit ; Interrupt SCI receive
sai_int org p:SAI_RDR jsr INT_RDR org p:SAI_TDE jsr INT_TDE org p:SAI_ROF jsr INT_ROF org p:SAI_TUF jsr INT_TUF
essi_int org p:essi0_rdf jsr Comp_0 nop org p:essi0_roe
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TDA7590
movep x:M_SSISR0,a0 movep x:M_RX0,y:(r0)+ org p:essi0_rls nop nop org p:essi0_tde jsr clr_tde0 nop org p:essi0_tue jsr clr_tue0 nop org p:essi0_tls nop nop
Appendix 1
timer_int org p:Timer0_tcf jsr INT_TMR0_tcf org p:Timer0_tof jsr INT_TMR0_tof org p:Timer1_tcf jsr INT_TMR1_tcf org p:Timer1_tof jsr INT_TMR1_tof org p:Timer2_tcf jsr INT_TMR2_tcf org p:Timer2_tof jsr INT_TMR2_tof
org x:0 states dsm ntaps
org y:0 coef dc .1,.3,-.1,.2
org p:$100 start ; setup external memory for sync with testbench ;-----------------------------------------------------------------------; Initialise Core
;------------------------------------------------------------------------
clr clr move move ori movep movep
a b #$0,r0 #$fff,m0 #$3,mr #INIT_IPR_C,x:IPR_C #INIT_IPR_P,x:IPR_P ; mask interrupts ; set CORE interrupt priorities ; set PERIPHERAL interrupt priorities
;-----------------------------------------------------------------------; Initialise PLL
;-----------------------------------------------------------------------init_pll movep jclr #INIT_PLL_CSR,x:PLL_CSR #LOCK,x:<31/40
Appendix 1
movep bset movep #INIT_PLL_FCR,x:PLL_FCR #FRACEN,x:<TDA7590
IF 1 ;-----------------------------------------------------------------------; Initialise CODEC
;-----------------------------------------------------------------------init_codec movep #INIT_CODEC_CSR,x:CODEC_CSR ; initialise CODEC control/status reg
;-----------------------------------------------------------------------; Initialise SAI
;-----------------------------------------------------------------------; The receiver and transmitter control/status register are configured the same for simplicity only. ; Master mode , 24-bit word-size , MSB first , Low word clock = left word , Neg bit-clk polarity , ; Non i2s format , init_sai movep movep #INIT_SAI_TCS,y:SAI_TCS #INIT_SAI_RCS,y:SAI_RCS ; initialise transmit control/status reg ; initialise receiver control/status reg (For 32-bit words) First bit x 8 , Interrupts enabled.
;-----------------------------------------------------------------------; Enable gpios for HI ;-----------------------------------------------------------------------bset bset bset bset ENDIF #GPIO0_DIR,x:GPIOCTRL #GPIO0_DIR,x:GPIODIR #GPIO1_DIR,x:GPIOCTRL #GPIO1_DIR,x:GPIODIR ; Setup HI pin for GPIO mode ; Setup GPIO as output ; Setup HI pin for GPIO mode ; Setup GPIO as output
;-----------------------------------------------------------------------; Initialize ESSI0 ;-----------------------------------------------------------------------IF 1 init_essi movep #$181801,x:M_CRA0 ; cra0_addr, 24'b010110000001100000011110 ; The divider control is set to 1 (2 words per frame) ; for Normal mode, bits are left aligned to bit 23. ; length is set to 24 bits.PM = 1 -> Fcore/4. Word
movep #$fc113e,x:M_CRB0 ; crb0_addr, 24'b111111000001010100111110 ; The receive exception and transmit exception interrupts ; are enabled as are receive last slot and transmit last ; slot. It is set in the synchronous normal mode. Data and ; frame sync are clocked out on the rising edge of the clock. ; Frame sync polarity is positive and occurs together with the ; the first bit of data from the first slot. ; first. SC2 o/p SC1 o/p SC0 o/p Enable_pins ;-----------------------------------------------------------------------move #$01c000,x0 ; ; ; // Enable TX2/TX1/TX0 (ESSI 0) MSB is shifted
movep x:M_CRB0,b1 or x0,b1
movep #$00003f,x:M_PCRC ; // ALL Pins are ESSI. ; check that all pins are enabled rep nop #$05
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TDA7590
movep b1,x:M_CRB0
Appendix 1
ENDIF
IF 1 ;-----------------------------------------------------------------------; Enable gpios for TIMER ;------------------------------------------------------------------------
init_gpio ; ; movep movep Movep Movep #$000000,x:<;-----------------------------------------------------------------------; Initialise Timer
;------------------------------------------------------------------------
init_timer bclr #0,x:M_TCSR0 bclr #0,x:M_TCSR1 bclr #0,x:M_TCSR2 ; Disable Timer0 ; Disable Timer1 ; Disable Timer2
movep #INIT_TCSR0,x:<; Timer0 enable at mode 0 + reload ; Initial value of the timer counter ; Initial value of the timer counter ; Number of CLK/2 cycles until a trigger is generated
movep #INIT_TCSR1,x:<; Timer1 enable at mode 0 + reload ; Initial value of the timer counter ; Initial value of the timer counter ; Number of CLK/2 cycles until a trigger is generated
movep #INIT_TCSR2,x:<; Timer2 enable at mode 0 + reload ; Initial value of the timer counter ; Initial value of the timer counter ; Number of CLK/2 cycles until a trigger is generated
;-----------------------------------------------------------------------; Initialise Expansion Port and Flex Memory
;-----------------------------------------------------------------------init_expport movep movep #INIT_AAR0,x:EXP_AAR0 #INIT_BCR,x:EXP_BCR ; initialise AAR0 control/status reg ; initialise BCR reg
ENDIF
;-----------------------------------------------------------------------; Initialise SCI
;-----------------------------------------------------------------------IF 1 init_sci movep movep movep #$E,x:SCCR_ADR #$7,x:PCRE_ADR #$11b02,x:SCR_ADR
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Appendix 1
ENDIF
TDA7590
;-----------------------------------------------------------------------; Enable interrupts ;------------------------------------------------------------------------
Andi #$fc,mr
; set DSP interrupt priority level to 0 ; Sets the Interrupt Mask bits in the SR ; to [00] (No exceptions masked)
IF 1 Bset #0,x:M_TCSR0 Bset #0,x:M_TCSR1 Bset #0,x:M_TCSR2 ENDIF ; Enable Timer0 ; Enable Timer1 ; Enable Timer2
move move move move
#states,r3 #ntaps-1,m3 #coef,r4 #ntaps-1,m4
;-----------------------------------------------------------------------; Processor Loop ;------------------------------------------------------------------------
IF 0 LOOP ; bset nop nop nop nop nop nop nop nop nop nop nop nop jmp LOOP ENDIF #12,x:SCR_ADR ; start SCI transmit
IF 1 LOOP ; bset mac move move move #12,x:SCR_ADR x0,y0,a #$AAAAAA,x0 x0,x:$CAAAAA x0,x:GPIODAT ; send data to expansion port ; move PORTB pins x:(r3)+,x0 y:(r4)+,y0 ; start SCI transmit ; generates variations on mean value of DAC
bset mac move move move
#12,x:SCR_ADR x0,y0,a #$555555,x0 x0,x:$C55555 x0,x:GPIODAT x:(r3)+,x0 y:(r4)+,y0
; start SCI transmit ; generates variations on mean value of DAC
; send data to expansion port ; move PORTB pins
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bset mac move move move #12,x:SCR_ADR x0,y0,a #$AAAAAA,x0 x0,x:$CAAAAA x0,x:GPIODAT ; send data to expansion port ; move PORTB pins x:(r3)+,x0 y:(r4)+,y0 ; start SCI transmit ; generates variations on mean value of DAC
Appendix 1
bset mac move move move
#12,x:SCR_ADR x0,y0,a #$555555,x0 x0,x:$C55555 x0,x:GPIODAT x:(r3)+,x0 y:(r4)+,y0
; start SCI transmit ; generates variations on mean value of DAC
; send data to expansion port ; move PORTB pins
jmp LOOP
ENDIF
;-----------------------------------------------------------------------; Interrupt Service Routines
;------------------------------------------------------------------------
;SAI ;-----------------------------------------------------------------------INT_TDE ; The transmitter data empty flag is cleared as soon ; as the last move is performed Movep a,y:<INT_RDR
; The receiver data ready flag is cleared as soon ; as the last move is performed
movep move nop nop movep move rti
y:<; Move Channel 0 received LEFT data to x-memory.
y:<; Move channel 0 received RIGHT data to y-memory.
INT_ROF bset bclr rti #16,y:SAI_RCS #16,y:SAI_RCS
INT_TUF bset bclr rti #16,y:SAI_TCS #16,y:SAI_RCS
;TIMER
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Appendix 1
;-----------------------------------------------------------------------INT_TMR0_tcf ; bchg bchg nop rti #0,x:PDRC #13,x:M_TCSR0 ; toggle pin12 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2) ; toggle TIO0 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2)
TDA7590
INT_TMR0_tof nop nop rti
INT_TMR1_tcf ; bchg bchg nop rti #1,x:PDRC #13,x:M_TCSR1 ; toggle pin4 Fout=Fin/((TPLR+1)*(TCPR+1)*2) ; toggle TIO1 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2)
INT_TMR1_tof nop nop rti
INT_TMR2_tcf ; bchg bchg nop rti #2,x:PDRC #13,x:M_TCSR2 ; toggle pin3 Fout=Fin/((TPLR+1)*(TCPR+1)*2)
; toggle TIO2 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2)
INT_TMR2_tof nop nop rti
;ESSI ;-----------------------------------------------------------------------clr_tde0 movep move movep move movep move rti r1,x:M_TX00 (r1)+ r1,x:M_TX01 (r1)+ r1,x:M_TX02 (r1)+
clr_tue0 movep movep move movep move movep move rti x:M_SSISR0,a0 r1,x:M_TX00 (r1)+ r1,x:M_TX01 (r1)+ r1,x:M_TX02 (1)+
Comp_0 rti
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TDA7590
Appendix 1
Clr_gpio bclr rti #0,x:M_PDRE
Comp_1 rti
;SCI ;-----------------------------------------------------------------------INT_SCIR move movep ; ; move move rti x:SRXL_ADR,x0 #$3f02,x:SCR_ADR x0,x:(r1)+ x0,x:$C00000
INT_SCIT ; movep movep ; L3 jclr movep rti #0,x:<INT_SCIE jclr L2 jclr movep NO_FRA nop move rti x:SRXL_ADR,x0 #0,x:<37/40
Package information
TDA7590
9 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 3. TQFP144 Mechanical data & package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D2 D3 e E E1 E2 E3 L L1 K ccc 0.45 21.80 19.80 2.00 17.50 0.60 1.00 0.75 0.018 0.05 0.95 0.17 0.09 21.80 19.80 2.00 17.50 0.50 22.00 20.00 22.20 20.20 0.858 0.779 0.079 0.689 0.024 0.0393 0.030 22.00 20.00 1.00 0.22 TYP. MAX. 1.20 0.15 1.05 0.27 0.20 22.20 20.20 0.002 0.037 0.007 0.003 0.858 0.779 0.079 0.689 0.020 0.866 0.787 0.874 0.795 0.866 0.787 0.039 0.009 MIN. TYP. MAX. 0.047 0.006 0.041 0.011 0.008 0.874 0.795 inch
OUTLINE AND MECHANICAL DATA
3.5 (min.), 7(max.) 0.08 0.03
TQFP144 (20x20x1.0mm exposed Pad Down)
Note 1: Exact shape of each corner is optional.
7386636
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Revision history
10
Revision history
Table 7.
Date 11-Apr-2006
Document revision history
Revision 1 Initial release. Changes
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TDA7590
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